In this specification, the following technical references are cited, and document numbers given thereto are hereinafter used for the sake of simplicity [Document 1]: Japanese Unexamined Patent Publication No. 6 (1994)-309872 (corresponding to U.S. Pat. No. 5,412,605); [Document 2]: VLSI Memory, pp. 161–167, K. Ito, Baihuukan, 1st Issue, Nov. 5, 1994; [Document 3]: T. Yamada, et al., ISSCC91 Dig. Tech. Papers, pp. 108–109, 1991; [Document 4]: H. Hidaka, et al., IEEE Journal of Solid State Circuit, Vol 27, No. 7, (1992), pp. 1020–1027; [Document 5]: Japanese Unexamined Patent Publication No. 63 (1988)-211191; [Document 6]: S. Eto, et al., ISSCC98 Dig. Tech. Papers, pp. 82–83, 1998.
In [Document 1], there is disclosed a technique of stabilizing sense amplifier operation under condition of a reduced power supply voltage in a DRAM by applying a voltage having a potential difference with respect to a final amplification voltage such as GND (e.g., a negative voltage lower than GND) to a source node of a CMOS sense amplifier. This technique is referred to as an “over-driving” scheme since there is provided a time interval during which the sense amplifier is driven by the voltage having a potential difference with respect to the final amplification voltage on a bit line.
[Document 2] is mainly concerned with the technologies of dynamic random access memories (DRAMs), and on pages 161 to 167 thereof, a sense circuit for amplifying a minuscule signal supplied from a memory cell is explained. In particular, pages 163 and 164 describe a method of driving a plurality of sense amplifiers at high speed, under the section title of “(2) Current-Distribution-Type Sense Amplifier Driving.” More specifically, according to this method, a sense amplifier driving power voltage (equal to a final amplification voltage on a data line) is supplied in a meshed wiring arrangement, and a plurality of sense amplifiers are driven through one of driving MOSFETs disposed distributively (e.g., four sense amplifiers are driven through one driving MOSFET). [Document 3] and [Document 4] are cited in [Document 2] as the original technical literature proposing the above-mentioned method.
For the purpose of making it possible to implement an over-driving circuit for a large-capacity DRAM to be operated on a low power supply voltage, the inventors have examined some aspects of practicable arrangements of a sense amplifier and an over-driving drive circuit therefor in the DRAM prior to preparing this patent application.
FIG. 25 shows an essential circuit part of the DRAM containing an over-driving drive circuit which has been examined by the inventors prior to preparation of this patent application. The over-driving drive circuit is designed to over-drive a P-side common source line CSP using a voltage VDH higher than a high-level voltage “H” on a data line (VDL) In the over-driving drive circuit, an over-driving voltage VDH is supplied from a terminal of the P-side common source line CSP through a PMOS transistor QDP1 located thereat. In consideration of addition of the over-driving circuit, it is desirable to provide the over-driving drive circuit at a terminal of the CSP line as in the above-stated arrangement for reduction in circuit area.
FIG. 26 shows operating waveforms appearing on the common source line and data line in sense amplifier operation. It is herein assumed that the data line and common source line are precharged with VDL/2 before a sense amplifier starts amplification. Under condition that SP1 is set to a low level to put QDP1 into conduction and the common source line CSP is supplied with the VDH, there are located SAn at the nearest position to a VDH supply node and SA1 at the farthest position therefrom. An over-driving time period Tod representing a duration for which the QDP1 is put into conduction is set so that the “H” level side of the data line will reach the VDL at high speed, not exceeding the VDL.
FIG. 26 (a) shows a case where the Tod is optimized with respect to the SAn which is located at the nearest position to a sense driver corresponding to the VDH supply node, and FIG. 26 (b) shows a case where the Tod is optimized with respect to the SA1 which is located at the farthest position therefrom. As shown in FIG. 26 (a), where the Tod is optimized with respect to the nearest position, a voltage drop occurs on the common source line due to a current supplied from the common source line to each SA in the initial period of sense operation. On the other hand, at the farthest position, an OFF state takes place before a sufficiently high level of voltage (CSP (1)) is not reached, resulting in a sufficiently high effective gate voltage not being attained as required. That is to say, data lines (D1t, D1b) are put in a low-speed operation state. By way of contrast, as shown in FIG. 26 (b), where the Tod is optimized with respect to the farthest position (SA1), the effect of over-driving becomes too high at the nearest position, causing a data line voltage to exceed the VDL. This results in an increase in power consumption. As mentioned above, the inventors have found that a voltage drop due to resistance on a common source line causes a decrease in sense operation speed or an increase in power consumption, depending on the position of each sense amplifier.
While a current concentration to a common source line of sense amplifiers and an effect on voltage attained thereby are discussed in [Document 2] to [Document 4], no consideration is given to application to an over-driving circuit for the sense amplifiers therein.
It is therefore an object of the present invention to provide a semiconductor device in which non-uniformity in over-driving among a plurality of sense amplifiers is eliminated. Another object of the present invention is to provide a semiconductor device in which an increase in layout area including a plurality of sense amplifiers is reduced while eliminating non-uniformity in over-driving.